User Contributed MET/CAL PROCEDURE ============================================================================= INSTRUMENT: HP 6632A:System DC Power Supply DATE: 22-Feb-96 AUTHOR: User Contributed REVISION: 0 ADJUSTMENT THRESHOLD: 70% NUMBER OF TESTS: 43 NUMBER OF LINES: 365 CONFIGURATION: Datron 1281 STANDARD: DTB Metered Variac STANDARD: EPC HS 5-500 STANDARD: Transistor Devices DLP 50 ============================================================================= STEP FSC RANGE NOMINAL TOLERANCE MOD1 MOD2 3 4 CON 1.001 ASK+ X 1.002 ASK- R N P F W 1.003 HEAD ÍÍ INITIAL CONDITIONS ÍÍ 1.004 DISP The following Standard test equipment is needed: 1.004 DISP 1. Metered vaiac DTB # 2-172 1.004 DISP 2. Transistor Devices DLP 50-150-3000A 1.004 DISP 3. EPC HS 5-500 5 Amp Shunt DTB # 14-107 1.005 DISP Connect the test equipment as follows: 1.005 DISP UUT AC line to variac. 1.005 DISP System IEEE port 1 to UUT IEEE connector. 1.006 STD DTB Metered Variac 1.007 DISP Adjust variac for an AC voltmeter reading of 115VAC. 1.008 DISP ÿ Connect the 1281 and the UUT as follows: 1.008 DISP ÿ [27][91]1m 1281 TO 6633A 1.008 DISP ÿ INPUT HI ÄÄÄÄÄÄÄÄÄ FRONT OUTPUT + 1.008 DISP ÿ INPUT LO ÄÄÄÄÄÄÄÄÄ FRONT OUTPUT - 1.009 HEAD {} 1.010 HEAD {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 1.011 HEAD {º VOLTAGE PROGRAMING ACCURACY TEST º} 1.012 HEAD {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 1.013 HEAD {}ÍÍ VOLTAGE PROGRAMING ACCURACY TEST ÍÍ 1.014 JMP 2.001 1.015 EVAL 2.001 IEEE CLR; 2.002 IEEE VSET 1; 2.003 IEEE OUT 1; 2.004 IEEE [@1281]DCV AUTO 2.005 IEEE [@1281][D2000]RDG?[I] 2.006 ACC 2 1.000V 6P% 0.2P/ 2.007 MEME 2.008 MEMC V 0.05% 0.01U #! Test Tol 0.0105, Sys Tol 6.4e-006, TUR 1640.625 (>= 4.00). 3.001 IEEE VSET 2; 3.002 IEEE [@1281][D2000]RDG?[I] 3.003 ACC 20 2.000V 6P% 0.1P/ 3.004 MEME 3.005 MEMC V 0.05% 0.01U #! Test Tol 0.011, Sys Tol 1.4e-005, TUR 785.714 (>= 4.00). 4.001 IEEE VSET 3; 4.002 IEEE [@1281][D2000]RDG?[I] 4.003 ACC 20 3.000V 6P% 0.1P/ 4.004 MEME 4.005 MEMC V 0.05% 0.01U #! Test Tol 0.0115, Sys Tol 2e-005, TUR 575.000 (>= 4.00). 5.001 IEEE VSET 4; 5.002 IEEE [@1281][D2000]RDG?[I] 5.003 ACC 20 4.000V 6P% 0.1P/ 5.004 MEME 5.005 MEMC V 0.05% 0.01U #! Test Tol 0.012, Sys Tol 2.6e-005, TUR 461.538 (>= 4.00). 6.001 IEEE VSET 5; 6.002 IEEE [@1281][D2000]RDG?[I] 6.003 ACC 20 5.000V 6P% 0.1P/ 6.004 MEME 6.005 MEMC V 0.05% 0.01U #! Test Tol 0.0125, Sys Tol 3.2e-005, TUR 390.625 (>= 4.00). 7.001 IEEE VSET 6; 7.002 IEEE [@1281][D2000]RDG?[I] 7.003 ACC 20 6.000V 6P% 0.1P/ 7.004 MEME 7.005 MEMC V 0.05% 0.01U #! Test Tol 0.013, Sys Tol 3.8e-005, TUR 342.105 (>= 4.00). 8.001 IEEE VSET 7; 8.002 IEEE [@1281][D2000]RDG?[I] 8.003 ACC 20 7.000V 6P% 0.1P/ 8.004 MEME 8.005 MEMC V 0.05% 0.01U #! Test Tol 0.0135, Sys Tol 4.4e-005, TUR 306.818 (>= 4.00). 9.001 IEEE VSET 8; 9.002 IEEE [@1281][D2000]RDG?[I] 9.003 ACC 20 8.000V 6P% 0.1P/ 9.004 MEME 9.005 MEMC V 0.05% 0.01U #! Test Tol 0.014, Sys Tol 5e-005, TUR 280.000 (>= 4.00). 10.001 IEEE VSET 9; 10.002 IEEE [@1281][D2000]RDG?[I] 10.003 ACC 20 9.000V 6P% 0.1P/ 10.004 MEME 10.005 MEMC V 0.05% 0.01U #! Test Tol 0.0145, Sys Tol 5.6e-005, TUR 258.929 (>= 4.00). 11.001 IEEE VSET 10; 11.002 IEEE [@1281][D2000]RDG?[I] 11.003 ACC 20 10.000V 6P% 0.1P/ 11.004 MEME 11.005 MEMC V 0.05% 0.01U #! Test Tol 0.015, Sys Tol 6.2e-005, TUR 241.935 (>= 4.00). 12.001 IEEE VSET 20; 12.002 IEEE [@1281][D2000]RDG?[I] 12.003 ACC 200 20.000V 10P% 0.2P/ 12.004 MEME 12.005 MEMC V 0.05% 0.01U #! Test Tol 0.02, Sys Tol 0.00024, TUR 83.333 (>= 4.00). 13.001 HEAD {} 13.002 HEAD {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 13.003 HEAD {º VOLTAGE READBACK ACCURACY TEST º} 13.004 HEAD {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 13.005 HEAD {}ÍÍ VOLTAGE READBACK ACCURACY TEST ÍÍ 13.006 JMP 14.001 13.007 EVAL 14.001 IEEE CLR; 14.002 IEEE VSET 1; 14.003 IEEE OUT 1;[D1000] 14.004 IEEE VOUT?;[I] 14.005 MEMC 1.000V 0.07% 0.015U #! T.U.R. not calculated because System Uncertainty not available. 15.001 IEEE VSET 2;[D1000] 15.002 IEEE VOUT?;[I] 15.003 MEMC 2.000V 0.07% 0.015U #! T.U.R. not calculated because System Uncertainty not available. 16.001 IEEE VSET 3;[D1000] 16.002 IEEE VOUT?;[I] 16.003 MEMC 3.000V 0.07% 0.015U #! T.U.R. not calculated because System Uncertainty not available. 17.001 IEEE VSET 4;[D1000] 17.002 IEEE VOUT?;[I] 17.003 MEMC 4.000V 0.07% 0.015U #! T.U.R. not calculated because System Uncertainty not available. 18.001 IEEE VSET 5;[D1000] 18.002 IEEE VOUT?;[I] 18.003 MEMC 5.000V 0.07% 0.015U #! T.U.R. not calculated because System Uncertainty not available. 19.001 IEEE VSET 6;[D1000] 19.002 IEEE VOUT?;[I] 19.003 MEMC 6.000V 0.07% 0.015U #! T.U.R. not calculated because System Uncertainty not available. 20.001 IEEE VSET 7;[D1000] 20.002 IEEE VOUT?;[I] 20.003 MEMC 7.000V 0.07% 0.015U #! T.U.R. not calculated because System Uncertainty not available. 21.001 IEEE VSET 8;[D1000] 21.002 IEEE VOUT?;[I] 21.003 MEMC 8.000V 0.07% 0.015U #! T.U.R. not calculated because System Uncertainty not available. 22.001 IEEE VSET 9;[D1000] 22.002 IEEE VOUT?;[I] 22.003 MEMC 9.000V 0.07% 0.015U #! T.U.R. not calculated because System Uncertainty not available. 23.001 IEEE VSET 10;[D1000] 23.002 IEEE VOUT?;[I] 23.003 MEMC 10.000V 0.07% 0.015U #! T.U.R. not calculated because System Uncertainty not available. 24.001 IEEE VSET 20;[D1000] 24.002 IEEE VOUT?;[I] 24.003 MEMC 20.000V 0.07% 0.015U #! T.U.R. not calculated because System Uncertainty not available. 25.001 IEEE CLR; 25.002 IEEE OUT 0; 25.003 DISP Disconnect the test setup. 25.004 HEAD {} 25.005 HEAD {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 25.006 HEAD {º CURRENT PROGRAMMING VERIFICATION TEST º} 25.007 HEAD {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 25.008 HEAD {}ÍÍ CURRENT PROGRAMMING VERIFICATION TEST ÍÍ 25.009 STD EPC HS 5-500 25.010 JMP 26.001 25.011 EVAL 26.001 DISP ÿ Connect the HS 5-500 and the UUT as follows: 26.001 DISP ÿ [27][91]1m HS 5-500 TO 6633A 26.001 DISP ÿ INPUT HI ÄÄÄÄÄÄÄÄÄ REAR OUTPUT + 26.001 DISP ÿ INPUT LO ÄÄÄÄÄÄÄÄÄ REAR OUTPUT - 26.002 DISP ÿ Connect the HS 5-500 and the 1281 as follows: 26.002 DISP ÿ [27][91]1m HS 5-500 TO 1281 26.002 DISP ÿ SENSE TERMINAL HI ÄÄÄÄÄÄÄÄÄ INPUT HI 26.002 DISP ÿ SENSE TERMINAL LO ÄÄÄÄÄÄÄÄÄ INPUT LO 26.003 MEMI Use keyboard to enter acctual shunt resistance in ohms: 26.004 MEME 26.005 MATH M[1] = MEM1 26.006 IEEE VSET 2; 26.007 IEEE ISET 1;[D1000] 26.008 IEEE OUT 1; 26.009 IEEE [@1281][D2000]RDG?[I] #26.010 MEM/ 26.010 MATH MEM = MEM / M[1] #26.011 ACC 2 1.0000V 6P% 0.2P/ 26.011 MATH MEM1 = 1 26.012 MEME 26.013 MEMC A 0.15% 0.0020U #! Test Tol 0.0035, Sys Tol 6.4e-006, TUR 546.875 (>= 4.00). 27.001 MATH MEM1 = M[1] 27.002 IEEE ISET 2;[D1000] 27.003 IEEE [@1281][D2000]RDG?[I] #27.004 MEM/ 27.004 MATH MEM = MEM / M[1] #27.005 ACC 20 2.0000V 6P% 0.1P/ 27.005 MATH MEM1 = 2 27.006 MEME 27.007 MEMC A 0.15% 0.0020U #! Test Tol 0.005, Sys Tol 1.4e-005, TUR 357.143 (>= 4.00). 28.001 MATH MEM1 = M[1] 28.002 IEEE ISET 3;[D1000] 28.003 IEEE [@1281][D2000]RDG?[I] #28.004 MEM/ 28.004 MATH MEM = MEM / M[1] #28.005 ACC 20 3.0000V 6P% 0.1P/ 28.005 MATH MEM1 = 3 28.006 MEME 28.007 MEMC A 0.15% 0.0020U #! Test Tol 0.0065, Sys Tol 2e-005, TUR 325.000 (>= 4.00). 29.001 MATH MEM1 = M[1] 29.002 IEEE ISET 4;[D1000] 29.003 IEEE [@1281][D2000]RDG?[I] #29.004 MEM/ 29.004 MATH MEM = MEM / M[1] #29.005 ACC 20 4.0000V 6P% 0.1P/ 29.005 MATH MEM1 = 4 29.006 MEME 29.007 MEMC A 0.15% 0.0020U #! Test Tol 0.008, Sys Tol 2.6e-005, TUR 307.692 (>= 4.00). 30.001 MATH MEM1 = M[1] 30.002 IEEE ISET 5;[D1000] 30.003 IEEE [@1281][D2000]RDG?[I] #30.004 MEM/ 30.004 MATH MEM = MEM / M[1] #30.005 ACC 20 5.0000V 6P% 0.1P/ 30.005 MATH MEM1 = 5 30.006 MEME 30.007 MEMC A 0.15% 0.0020U #! Test Tol 0.0095, Sys Tol 3.2e-005, TUR 296.875 (>= 4.00). 31.001 IEEE CLR; 31.002 HEAD {} 31.003 HEAD {} 31.004 HEAD {} 31.005 HEAD {} 31.006 HEAD {} 31.007 HEAD {} 31.008 HEAD {} 31.009 HEAD {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 31.010 HEAD {º CURRENT READBACK ACCURACY TEST º} 31.011 HEAD {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 31.012 HEAD {}ÍÍ CURRENT READBACK ACCURACY ÍÍ 31.013 JMP 32.001 31.014 EVAL 32.001 IEEE VSET 2; 32.002 IEEE OUT 1; 32.003 IEEE ISET 1;[D1000] 32.004 IEEE IOUT?;[I] 32.005 MEMC 1.0000A 0.18% 0.009U #! T.U.R. not calculated because System Uncertainty not available. 33.001 IEEE ISET 2;[D1000] 33.002 IEEE IOUT?;[I] 33.003 MEMC 2.0000A 0.18% 0.009U #! T.U.R. not calculated because System Uncertainty not available. 34.001 IEEE ISET 3;[D1000] 34.002 IEEE IOUT?;[I] 34.003 MEMC 3.0000A 0.18% 0.009U #! T.U.R. not calculated because System Uncertainty not available. 35.001 IEEE ISET 4;[D1000] 35.002 IEEE IOUT?;[I] 35.003 MEMC 4.0000A 0.18% 0.009U #! T.U.R. not calculated because System Uncertainty not available. 36.001 IEEE ISET 5;[D1000] 36.002 IEEE IOUT?;[I] 36.003 MEMC 5.0000A 0.18% 0.009U #! T.U.R. not calculated because System Uncertainty not available. 37.001 IEEE CLR; 37.002 IEEE OUT 0; 37.003 DISP Disconnect the test setup. 37.004 HEAD {} 37.005 HEAD {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 37.006 HEAD {º RIPPLE AND NOISE TEST º} 37.007 HEAD {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 37.008 HEAD {}ÍÍ RIPPLE AND NOISE TEST ÍÍ 37.009 JMP 38.001 37.010 EVAL 38.001 DISP ÿ Connect the DLP 50 and the UUT as follows: 38.001 DISP ÿ [27][91]1m DLP 50 TO 6633A 38.001 DISP ÿ INPUT HI ÄÄÄÄÄÄÄÄÄ REAR OUTPUT + 38.001 DISP ÿ INPUT LO ÄÄÄÄÄÄÄÄÄ REAR OUTPUT - 38.002 DISP ÿ Connect the DPL 50 and the 1281 as follows: 38.002 DISP ÿ [27][91]1m 1281 TO 6633A 38.003 DISP ÿ INPUT HI ÄÄÄÄÄÄÄÄÄ REAR OUTPUT +S 38.003 DISP ÿ INPUT LO ÄÄÄÄÄÄÄÄÄ REAR OUTPUT -S 38.004 STD Transistor Devices DLP 50 38.005 DISP Set the DLP 50 front panel controls as follows: 38.005 DISP VOLTS RANGE ........................................ 60V 38.005 DISP AMPS RANGE ......................................... 18A 38.005 DISP MODE ............................................. 0-30A 38.005 DISP DC switch .......................................... OFF 38.005 DISP LOAD ADJUST COARSE/FINE ...................... fully ccw 38.006 IEEE VSET 20; 38.007 IEEE ISET 5.04; 38.008 IEEE OUT 1; 38.009 DISP Set the DLP 50 front panel controls as follows: 38.009 DISP DC switch ........................................... ON 38.010 DISP Adjust DLP 50 COARSE and FINE LOAD ADJUST controls 38.010 DISP for a UUT reading of 5 amps. 38.010 DISP 38.010 DISP NOTE: Be careful not to exceed 5 amps or UUT will 38.010 DISP cross-over into constant current mode. If this occurs, 38.010 DISP go to local mode and make necessary corrections 38.010 DISP manually. 38.011 DISP Adjust variac for an reading of 115VAC. 38.012 IEEE [@1281] ACV AUTO 38.013 IEEE [@1281] [D5000]RDG?[I] 38.014 MEM* 1000 38.015 ACC 200 0.000mVRMS 200P% 20P/ 38.016 MEME 38.017 MEMC mVRMS 0.300U 60H #! Test Tol 0.3, Sys Tol 0.004, TUR 75.000 (>= 4.00). 39.001 HEAD {} 39.002 HEAD {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 39.003 HEAD {º LINE REGULATION TEST º} 39.004 HEAD {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 39.005 HEAD {}ÍÍ LINE REGULATION TEST ÍÍ 39.006 JMP 40.001 39.007 EVAL 40.001 DISP Adjust variac for an reading of 104VAC. 40.002 IEEE [@1281] DCV AUTO 40.003 IEEE [@1281] [D2000]RDG?[I] 40.004 MEME 40.005 DISP Adjust variac for an reading of 127VAC. 40.006 IEEE [@1281] [D2000]RDG?[I] 40.007 MEM- 40.008 MEM* 1000 40.009 ACC 200 0.000mV 7P% 0.5P/ 40.010 MEME 40.011 MEMC mV 0.500U #! Test Tol 0.5, Sys Tol 0.0001, TUR 5000.000 (>= 4.00). 41.001 DISP Adjust variac for an reading of 115VAC. 41.002 HEAD {} 41.003 HEAD {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 41.004 HEAD {º LOAD REGULATION TEST º} 41.005 HEAD {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 41.006 HEAD {}ÍÍ LOAD REGULATION TEST ÍÍ 41.007 JMP 42.002 41.008 EVAL 42.001 DISP Set the DLP 50 front panel controls as follows: 42.001 DISP DC switch ........................................... ON 42.002 IEEE [@1281] [D2000]RDG?[I] 42.003 MEME 42.004 DISP Set the DLP 50 front panel controls as follows: 42.004 DISP DC switch .......................................... OFF 42.005 IEEE [@1281] [D2000]RDG?[I] 42.006 MEM- 42.007 MEM* 1000 42.008 ACC 200 0.000mV 7P% 0.5P/ 42.009 MEME 42.010 MEMC mV 2.000U #! Test Tol 2, Sys Tol 0.0001, TUR 20000.000 (>= 4.00). 43.001 IEEE CLR; 43.002 HEAD {} 43.003 DISP {ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»} 43.003 DISP {º THIS COMPLETES THE VERIFICATION º} 43.003 DISP {ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ} 43.004 END #! T.U.R.s less than 4.00: 0 #! T.U.R.s estimated using RANGE value: 0 #! T.U.R.s not calculated (ASK- U): 0 #! T.U.R.s not computable at compile time: 17 #! FOR JUSTIFICATION REFER TO COMMENTS FOLLOWING EACH TEST IN THIS LISTING.